During
front-end design, a solution is architected and implemented, typically in
Register Transfer Logic (RTL), and might incorporate existing components such
as memory and bus controllers. Some components, notably SRAMs and I/O pads,
might undergo only behavior modeling in RTL. Once the front-end RTL is final,
it is extensively tested and verified using simulators. Verification often
dominates the effort and cost of this initial hardware design step. Complex
components, or intellectual property (IP), such as processor cores, are usually
designed by experts and reused.
front-end design IP includes full-fledged cores such as RISC-V Rocket, OpenRISC, and LEON, as well as GPGPUs such as MIAOW, Nyami, and Nyuzi The opencores.org repository provides a wide assortment of modules, such as memory controllers, arithmetic logic units (ALUs), floating-point units (FPUs), USB controllers, and Ethernet controllers. lowRISC ) is an open source SoC effort. Occasionally, industry provides free IP for prototyping; for example, ARM provides the Cortex-M0 microcontroller, but not as modifiable open source. Some open source EDA tools have been developed by the community for front-end design. Examples include the Verilator simulator, and new frontend languages like Chisel and PyMTL.
Big technology companies have begun dabbling with RISC-V, which replaces proprietary know-how in a key part of the chip design process with a free standard that anyone can use. While it’s early days, this could create a new crop of processors that compete with Intel Corp. products and whittle away at the licensing business of Arm Holdings Plc. Google is using RISC-V in its OpenTitan project, which is developing security chips for data center servers and storage devices. Samsung said it will use SiFive designs in chips it’s making for mobile phone components

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