Skip to main content

OPEN SOURCE EFFORTS FOR FRONT END DESIGN

 

During front-end design, a solution is architected and implemented, typically in Register Transfer Logic (RTL), and might incorporate existing components such as memory and bus controllers. Some components, notably SRAMs and I/O pads, might undergo only behavior modeling in RTL. Once the front-end RTL is final, it is extensively tested and verified using simulators. Verification often dominates the effort and cost of this initial hardware design step. Complex components, or intellectual property (IP), such as processor cores, are usually designed by experts and reused.

front-end design IP includes full-fledged cores such as RISC-V Rocket, OpenRISC, and LEON, as well as GPGPUs such as MIAOW, Nyami, and Nyuzi  The opencores.org repository provides a wide assortment of modules, such as memory controllers, arithmetic logic units (ALUs), floating-point units (FPUs), USB controllers, and Ethernet controllers. lowRISC ) is an open source SoC effort. Occasionally, industry provides free IP for prototyping; for example, ARM provides the Cortex-M0 microcontroller, but not as modifiable open source. Some open source EDA tools have been developed by the community for front-end design. Examples include the Verilator simulator, and new frontend languages like Chisel and PyMTL.


Big technology companies have begun dabbling with RISC-V, which replaces proprietary know-how in a key part of the chip design process with a free standard that anyone can use. While it’s early days, this could create a new crop of processors that compete with Intel Corp. products and whittle away at the licensing business of Arm Holdings Plc. Google is using RISC-V in its OpenTitan project, which is developing security chips for data center servers and storage devices. Samsung said it will use SiFive designs in chips it’s making for mobile phone components

 

SiFive

Authored by Siddharth Sahoo

References:
1.) miaowgpu.org

2.)riscv.org

3.)nyuki.org

4.)Intel and Softbank Beware. Open Source Is Coming to the Chip Business By Ian King for Bloomberg


Comments

Post a Comment

Popular posts from this blog

THE NEED OF THE HOUR: Why the Semiconductor Industry requires an Open Source awakening?

Rise in silicon technology and the advances in hardware architecture have been instrumental in enabling new computing technologies and applications. But, with increasing chip-design costs and with the fall in the benefits of Moore’s law and Dennard scaling, the advances in silicon technology might well be grinding to a halt.  A DigiTimes report found out that foundry companies such as UMC (United Microelectronics), Global Foundries, and Vanguard International Semiconductor (VIS) have raised their 8-inch foundry quotes(In semiconductor industry it is custom to use foundry quotes, related to design requirements than an outright price) by 10-15% . Moore’s Law looked at the relation between process technology and economics. For half a century  the semiconductor industry pursued excellence in keeping with Moore's law. However  now the limitation to pack more transistors onto to a chip is a physical limitation called Dennard scaling which roughly states that  as transistor...
6 comments
Read more

OPEN SOURCE EFFORTS FOR BACK END DESIGN AND FABRICATION

  In this step, the RTL is transformed into a physical design. Synthesis tools are used to generate a gate-level netlist, which incorporates the physical component counterparts that were modeled in RTL, such as the SRAMs and I/O pads. The netlist is then made testable, and place-and-route EDA tools are used to physically place the gates and lay out the connecting wires. The physical design must adhere to strict design guidelines to ensure integrity and manufacturability, so it is verified at different stages. SRAM generator from cornell-ece5745.github.io Back-end modules like SRAMs and I/Os are closely tied to a foundry and technology node, building them requires specialized knowledge that is often proprietary. These modules are typically designed once by experts and reused. They are complex and essential design details are often unavailable and hence are scarce Open source back-end EDA tools include Berkeley ABC, Open Circuit Design, YOSYS, and Virtual Place and Route (VPR). B...
11 comments
Read more