EXISTING OPENSOURCE FOR FGPA AND SOC DESIGN

 FPGA stands for Field Programmable Gate Array which is a High-Speed Programmable logic consisting of Plenty of Input/Output options. FGPA's consist of an array of logic blocks which can be programmed into desired functionality and wired together , similar to logic gates.The FPGA configuration is generally specified using a hardware description language (HDL). They are mainly used in Digital Signal processing, parallel data processing, ASIC prototyping and more.  Xilinx, Lattice, Altera and Microsemi Corporation make up the vendor list for FPGA.

A SOC is in short terms an Integrated Circuit that integrates almost all components of a computer. With each SOC generation, the system becomes more intricate and complex to design and validate. Thus, The  goal of Open source frameworks here is to reduce the amount of effort put in by reusing and combining various Open Source Hardware components

Open source efforts have been fruitful for system hardware and circuit board design, but are lacking at the semiconductor level, particularly for system-on-chip (SoC) and field-programmable gate array (FPGA) design. Nevertheless, some tools do exist to make up the Open Source environment. Let's look at some of them in brief.

1.) Icarus Verilog: A HDL simulation/synthesis/translation tool which takes a Verilog code, a System Verilog Code or VHDL(limited support) as input and returns the output in the form of VVP(– Intermediate language used for simulation), VHDL(translation) and Verilog(simplification)

2.) Odin II : A HDL synthesis framework which comes with visualization support. Takes Verilog as Input and generates BLIF netlist(The technology mapped circuit to be implement on the target FPGA is specified as a Berkely Logic Interchange Format (BLIF) netlist.)

3.)Berkeley abc: Logic optimization tool.I/O is in the form of BLIF netlist.

4.)Yosys: HDL synthesis tool which comes with inbuilt Berkeley abc for logic optimization

5.)Archane PNR: This is a place and route tool which works in tandem with Yosys. Mapped netlist from Yosys is fed as input with textual representation of bitstream being the output

6.)IcePack: Open source assembler for iCE40 FPGA. Converts the textual representation of bitstream to binary representation

                                                              

iCE40 FPGA. Courtesy: Lattice Semiconductor

7.) IceStorm: Incorporates all 3: Yosys, Archane PNR and Ice Pack for design flow.

In Open Source platforms for SOC design,  we have ESP which is an open source research platform developed by Columbia University. The ESP architecture is a tile grid which as a distributed system is scalar, modular and heterogenous.ESP allows SoC designers to build FPGA based prototypes of complex SoCs by combining Open Source Hardware components that use the AXI protocol (e.g. ARIANE and NVDLA) with newly-designed components. ESP is also looking to expand towards front end for synthesizable RTL.

OpTiMSoC is an open-source framework that helps you implement your own manycore SOC by connecting tiles like processors and memories through a Network-on-Chip. It's project link is available on Github

For processor design we have the OpenRISC project which consists of  a free and open RISC instruction set architecture with DSP features, a set of free, open source implementations of the architecture, a complete set of free, open source software development tools, libraries, operating systems and applications and a variety of system-on-chip and system simulators

RISC processor

Authored by Samarth Srivastava

References:

1.)CAN OPEN SOURCE HARDWARE CRACK SEMICONDUCTOR INDUSTRY ECONOMICS- By Nicole Hemsoth for thenextplatform

2.)FPGA: Why So Few Open Source Drivers for Open Hardware? - By Martin Peres

3.)Kickstarting Semiconductor Innovation with Open Source Hardware by Gagan Gupta; Tony Nowatzki; Vinay Gangadhar; Karthikeyan Sankaralingam[Computer, Volume: 50, Issue: 6, 2017)

4) OpTimSoC.org

5.)ESP-Open SoC platform - Columbia University